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ISL6421A
Data Sheet March 9, 2006 FN9167.3
Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs
The ISL6421A is a highly integrated solution for providing power and control signals from advanced satellite set-top box (STB) modules to the low noise block (LNB). The internal architecture of this device contains a current-mode boost PWM and a low-noise linear regulator, along with the circuitry required for I2C device interfacing and for providing DiSEqCTM standard control signals to the LNB. A regulated output voltage is available at the output terminal (VOUT) to support the operation of the antenna port in advanced satellite STB applications. The regulated output may be set to either 13V or 18V by use of the voltage select command bit (VSEL) through the I2C bus. Additionally, to compensate for the voltage drop in the coaxial cable, the voltage may be increased by 1V with the line length compensation bit (LLC) feature. The device can be put into a standby mode by means of the enable bit (EN), this disables the PWM and Linear regulator combination and helps conserve power. The input to the linear regulator is derived from the current mode boost converter, such that the required voltage is the sum of the output voltage and the linear regulator drop (1.0V typical). This ensures that the power dissipation is minimized and maintains a constant voltage drop across the linear pass element, while permitting an adequate voltage range for tone injection. The device is capable of providing 450mA (typical). The overcurrent limit is either digitally or resistor programmable.
Features
* Switch-Mode Power Converter for Lowest Dissipation - Boost PWM with >92% Efficiency - Selectable 13V or 18V Outputs - Digital Cable Length Compensation (1V) - Vsw tracks Vout ensures low dissipation * I2C Compatible Interface for Remote Device Control - Registered Slave Address 0001 00XX - Fully Functional 3.3V, 5V Operation up to 400kHz * Built-In Tone Oscillator Factory Trimmed to 22kHz - Facilitates DiSEqCTM (EUTELSAT) Encoding - External Modulation input DSQIN * Internal Over Temperature Protection and Diagnostics * Internal Overload and Over Temperature Flags (Visible on I2C) * Output Back-Bias Protection to 24V * LNB Short-Circuit Protection and Diagnostics * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint * External Pins to Select 13V/18V Options * Pb-Free Available (RoHS Compliant)
Applications
* LNB Power Supply and Control for Satellite Set-Top Box
Pinout
NC
ISL6421A (QFN) TOP VIEW
CPVOUT CPSWIN VCC
References
* Tech Brief 389 (TB389) - "PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages"; Available on the Intersil website, www.intersil.com
24 CPSWOUT 23 NC 22 NC 21 NC 20 AGND 19 VOUT 18 DSQIN 17 TCAP
NC
NC
NC 29
32 PGND NC SGND SEL18V NC BYPASS PGND GATE 1 2 3 4 5 6 7 8 9 CS
31
30
NC 28
27
26
25
Ordering Information
PART NUMBER* ISL6421AER PART MARKING ISL6421AER TEMP. RANGE (C) PACKAGE PKG. DWG. #
-20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6421AERZ ISL6421AERZ -20 to 85 32 Ld 5x5 QFN L32.5x5 (Note) (Pb-free) *Add -T for tape and reel package. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
10 FB
11 COMP
12 VSW
13 NC
14 SDA
15 ADDR
16 SCL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Block Diagram
SEL18V OLF COUNTER OVERCURRENT PROTECTION LOGIC SCHEME 1 PWM LOGIC Q S CLK OLF PGND ISEL EN ENT CS AMP ILIM OTF + LLC SDA ADDR SDA ADDR SCL DCL OC
GATE
FB VREF
VSW
VOUT + OTF ON CHIP LINEAR UVLO POR SOFT-START BYPASS CPVOUT THERMAL SHUTDOWN
VCC
SGND
AGND
EN
TCAP
INT 5V SOFT-START
-
+
2
CS COMP
FN9167.3 March 9, 2006
I2 C INTERFACE
VSEL CLK
SCL DCL OSC. 220kHz
SLOPE COMPENSATION
BAND GAP REF VOLTAGE BGV REF VOLTAGE ADJ TONE INJ CKT
ISL6421A
/ 10 AND WAVE SHAPING
22kHz TONE
ENT DSQIN
CHARGE PUMP CPSWOUT
CPSWIN
Typical Application Schematic
3
ISL6421A
FN9167.3 March 9, 2006
NOTE: SGND and PGND to be shorted as close to U1 at layout
ISL6421A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V Logic Input Voltage Range (SDA, SCL, ENT) . . . . . . . . -0.5V to 7V Output Current . . . . . . . . . . . . . . . . . . . . Externally/Internally Limited
Thermal Information
Thermal Resistance (Notes 1, 2) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 35 6 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -40C to 150C For recommended soldering conditions, see Tech Brief TB389. NOTE: The device junction temperature should be kept below 150C. Thermal shut-down circuitry turns off the device if junction temperature exceeds +150C typically.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = 25C. EN = H, LLC = L, ENT = L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software description section for I2C access to the system. SYMBOL TEST CONDITIONS MIN 8 EN = L IIN EN = LLC = VSEL = ENT = H, No Load TYP 12 1.5 4.0 MAX 14 3.0 8.0 UNITS V mA mA
PARAMETER Operating Supply Voltage Range Standby Supply Current Supply Current UNDERVOLTAGE LOCKOUT Start Threshold Stop Threshold Start to Stop Hysteresis SOFT-START COMP Rise Time (Note 3) OUTPUT VOLTAGE Output Voltage (Note 4)
7.5 7.0 350
400
7.95 7.55 500
V V mV
(Note 5)
-
1024
-
Cycles
VOUT VOUT VOUT VOOU
VSEL = L, LLC = L VSEL = L, LLC = H VSEL = H, LLC = L VSEL = H, LLC = H VIN = 8V to 14V; VOUT = 13V VIN = 8V to 14V; VOUT = 18V
12.74 13.72 17.64 18.62 500 -
13.0 14.0 18.0 19.0 4.0 4.0 50 900 20 2.0
13.26 14.28 18.36 19.38 40.0 60.0 80 625 3.0
V V V V mV mV mV mA ms ms mA
Line Regulation
DVOUT
Load Regulation Dynamic Output Current Limiting Dynamic Overload Protection Off Time Dynamic Overload Protection On Time Output Backward Current 22kHz TONE Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time
DVOUT IMAX TOFF TON IOBK
IO = 12mA to 450mA DCL = L DCL = L, Output Shorted (Note 5)
EN = 0; VOBK = 24V
-
ftone Vtone dctone Tr, Tf
ENT = H ENT = H ENT = H ENT = H
20.0 500 40 5
22.0 680 50 8
24.0 900 60 14
kHz mV % s
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ISL6421A
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = 25C. EN = H, LLC = L, ENT = L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software description section for I2C access to the system. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER LINEAR REGULATOR Drop-out Voltage DSQIN PIN DSQIN pin logic Low DSQIN pin Logic HIGH DSQIN pin Input Current CURRENT SENSE Input Bias Current Overcurrent Threshold ERROR AMPLIFIER Open Loop Voltage Gain Gain Bandwidth Product PWM Maximum Duty Cycle Minimum Pulse Width OSCILLATOR Oscillator Frequency THERMAL PROTECTION Thermal Shutdown Temperature Shutdown Threshold Temperature Shutdown Hysteresis NOTES: 3. Internal digital soft-start.
Iout = 450mA (Note 5)
-
1.2
-
V
3.5 -
1
1.5V -
V V A
IBIAS Static current mode, DCL = H
325
700 400
500
nA mV
AOL
GBP
(Note 5) (Note 5)
70 10
88 -
-
dB MHz
90 (Note 5) -
93 20
-
% ns
fo
Fixed at (10)(ftone)
200
220
240
kHz
(Note 5) (Note 5)
-
150 20
-
C C
4. Voltage programming signals VSEL and LLC are implemented via the I2C bus. IO1 = IO2 = 500mA. 5. Guaranteed by design.
Functional Pin Description
SYMBOL SDA SCL VSW PGND CS SGND AGND TCAP BYPASS DSQIN Bidirectional data from/to I2C bus. Clock from I2C bus. Input of the linear post-regulator. Dedicated ground for the output gate driver of the PWM. Current sense input; connect Rsc at this pin for desired overcurrent value for the PWM. Small signal ground for the IC. Analog ground for the IC. Capacitor for setting rise and fall time of the output of the LNB. Use a capacitor value of 1F or higher. Bypass capacitor for internal 5V. When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for the LNB. FUNCTION
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ISL6421A
Functional Pin Description (Continued)
SYMBOL VCC GATE VOUT ADDRESS COMP FB CPVOUT, CPSWIN, CPSWOUT SEL18V Main power supply to the chip. This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET. This output is actively held low when Vcc is below the UVLO threshold. Output voltage for the LNB. Address pin to select two different addresses per voltage level at this pin. Error amp output used for compensation. Feedback pin for the PWM. Charge pump connections. When connected HIGH, this pin will change the output of the PWM to 18V. Only available on the QFN package option. FUNCTION
Functional Description
The ISL6421A is a single output voltage regulator controlled by an I2C bus, making it an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for a low noise block (LNB) are available simultaneously in any output configuration. The device utilizes a built-in DC/DC step-converter which, from a single supply source ranging from 8V to 14V, generates the voltage that enables the linear post-regulator to work with a minimum of dissipated power. An undervoltage lockout circuit disables the circuit when VCC drops below a fixed threshold (7.5V typ). ENT bit must be set LOW when the DSQIN pin is used for DiSEqC encoding.
Linear Regulator
The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.25F. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. When the device is put in the shutdown mode (EN = LOW), the PWM power block is disabled. When the regulator block is active (EN = HIGH), the output can be logic controlled to be 13V or 18V (typical) by means of the VSEL bit (Voltage Select) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DiSeqC standards. No further adjustment is required. The 22kHz oscillator can be controlled either by the I2C interface (ENT bit) or by a dedicated pin (DSQIN) that allows immediate DiSEqC data encoding for the LNB. All the functions of this IC are controlled via the I2C bus by writing to the system registers (SR). The same registers can be read back, and two bits will report the diagnostic status. The internal oscillator operates the converters at ten times the tone frequency. The device offers full I2C compatible functionality, 3.3V or 5V, and up to 400kHz operation. If the Tone Enable (ENT) bit is set LOW through I2C, then the DSQIN terminal activates the internal tone signal, modulating the dc output with a 0.3V, 22kHz, symmetrical waveform. The presence of this signal usually gives the LNB information about the band to be received. Burst coding of the 22kHz tone can be accomplished due to the fast response of the DSQIN input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols. When the ENT bit is set HIGH, a continuous 22kHz tone is generated regardless of the DSQIN pin logic status. The
Output Timing
The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47F to 2.2F, the rise and fall time would be 1.6ms to 7.6ms. Using a 0.47F capacitor insures the PWM stays below its overcurrent threshold when charging a 120F VSW filter cap during the worst case 13V to 19V transition. A typical value of 1.0F is recommended. This feature affects the programmed voltage rise and fall times.
Current Limiting
The current limiting block can operate either statically (simple current clamp) or dynamically. The threshold is between 500mA and 625mA. When the DCL (Dynamic Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically. That is, as soon as an overload is detected, the output is shut down for a time TOFF, typically
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FN9167.3 March 9, 2006
ISL6421A
900ms. Simultaneously the overload flag (OLF) bit of the system register is set to HIGH. After this time has elapsed, the output is resumed for a time TON = 20ms. During TON, the device output will be current limited to between 500mA and 625mA. At the end of TON, if the overload is still detected, the protection circuit will cycle again through TOFF and TON. At the end of a full TON, during which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical TON + TOFF time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up, when the dynamic protection is chosen. This can be solved by initiating a power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. The OLF bit will be LOW at the end of initial power-on soft-start. The static mode limit serves only to limit the peak current through the switching FET and cannot precisely set an average current limit. The sense resistor is calculated by the equation
0.4 R SC = -------I PK
I2C Bus Interface for ISL6421A
(Refer to Philips I2C Specification, Rev. 2.1) Data transmission from the main microprocessor to the ISL6421A and vice versa takes place through the 2 wires I2C bus interfaces, which consists of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stage of ISL6421A will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100kbits/s in the standard-mode or up to 400kbits/s in the fast-mode. The level of logic "0" and logic "1" is dependent of associated value of Vdd as per electrical specification table. One clock pulse is generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Refer to Figure 1.
SDA
SCL DATA LINE CHANGE STABLE OF DATA DATA VALID ALLOWED
where IPK is the peak current through the FET. This value should be greater that the normal operating peak current.
Thermal Resistance
This IC is protected against overheating. When the junction temperature exceeds 150C (typical), the step-up converter and the linear regulator are shut off and the overtemp flag (OTF) bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW, when the junction is cooled down to 130C (typical).
FIGURE 1. DATA VALIDITY
START and STOP Conditions
As shown in the Figure 2, START condition is a HIGH to LOW transition of the SDA line, while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line, while SCL is HIGH. A STOP condition must be sent before each START condition.
External Output Voltage Selection
The output voltage can be selected by the I2C bus. Additionally, the QFN package offers a pin (SEL18V) for independent 13V/18V output voltage selection. When using this pin, the I2C bits should be initialized to 13V status.
TABLE 1. I2C BITS 13V 13V SEL18V Low High O/P VOLTAGE 13V 18V
SDA
SCL S START CONDITION P STOP CONDITION
FIGURE 2. START AND STOP WAVEFORMS
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ISL6421A
Byte Format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB).
S0 0 0 TABLE 2. INTERFACE PROTOCOL 1 0 0 0 R/W ACK Data (8 bits) ACK P
TABLE 3. SYSTEM REGISTER 1 (SR1) R, W SR1 R, W DCL R, W X R, W ENT R, W LLC R, W VSEL R, W EN R OLF
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 3). The peripheral that acknowledges has to pull the SDA line down (LOW) during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.) The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6421A will not generate the acknowledge if the POWER OK signal from the UVLO is LOW.
SCL 1 SDA MSB START ACKNOWLEDGE FROM SLAVE 2 8 9
TABLE 4. SYSTEM REGISTER 2 (SR2) R, W SR2 R, W X R, W X R, W X R, W X R, W X R OTF R X
System Register Format
* R, W = Read and Write bit * R = Read-only bit All bits reset to 0 at Power-On
Transmitted Data (I2C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR1/SR2) of the ISL6421A via I2C bus. These will be written by the microprocessor as shown below. The spare bits of SR1/SR2 can be used for other functions.
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION SR DCL - ENT LLC VSEL EN OLF 0 0 X X X X X X X 0 1 0 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 FUNCTION SR1 is selected Vout1 = 13V, Vboost1 = 13V + Vdrop Vout1 = 18V, Vboost1 = 18V + Vdrop Vout1 = 14V, Vboost1 = 14V + Vdrop Vout1 = 19V, Vboost1 = 19V + Vdrop 22kHz tone is controlled by the DSQIN pin input 22kHz tone is ON, DSQIN pin input is disabled Dynamic current limit NOT selected Dynamic current limit selected PWM and Linear for channel 1 disabled
FIGURE 3. ACKNOWLEDGE ON THE I2C BUS 0
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. This approach, though, is less protected from error and decreases the noise immunity.
0 0 0 0
ISL6421A Software Description
Interface Protocol
The interface protocol is comprised of the following, as shown below in Table 2: * A start condition (S) * A chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I2C slave address for the ISL6421A is 0001 00XX) * A sequence of data (1 byte + Acknowledge) * A stop condition (P)
0 0 0
1 0 X
X X X X X X
1 1 0
SR 1
X
X
X
X
X
OTF X
-
FUNCTION
X SR2 is selected; to read OTF flag.
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ISL6421A
Received Data (I2C Bus Read Mode)
The ISL6421A can provide to the master a copy of the System Register information via the I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following Master generated clock bits, the ISL6421A issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: * Acknowledge the reception, starting in this way the transmission of another byte from the ISL6421A. * Not acknowledge, stopping the read mode communication. While the whole register is read back by the microprocessor, only the two read-only bits, OLF and OTF, convey diagnostic information about the ISL6421A.
TABLE 6. READING SYSTEM REGISTERS DCL ISEL ENT LLC VSEL EN OTF OLF These bits are read as they were after the last write operation. 0 1 0 1 FUNCTION Tj 130C, Normal operation Tj > 150C, Power blocks disabled Iout < Imax, Normal operation Iout > Imax, Overload protection triggered
Power-On I2C Interface Reset
The I2C interface built into the ISL6421A is automatically reset at power-on. The I2C interface block will receive a Power OK logic signal from the UVLO circuit. This signal will go HIGH when chip power is OK. As long as this signal is LOW, the interface will not respond to any I2C commands and the system register SR is initialized to all zeros, thus keeping the power blocks disabled. Once Vcc rises above the UVLO level, the POWER OK signal given to the I2C interface block will be HIGH, the I2C interface becomes operative and the SR can be configured by the main microprocessor. About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the Power-On reset circuit. (I2C comes up with EN = 0, EN goes HIGH at the same time as (or later than) all other I2C data for the PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND forces the chip I2C interface address to 0001000; applying a voltage >2.7V forces the address to 0001001, as shown below.
TABLE 7. ADDRESS PIN CHARACTERISTICS Vaddr Vaddr-1 "0001000" Vaddr-2 "0001001" MIN 0V 2.7V TYP MAX 2.0V 5.0V
I2C Electrical Specifications
TABLE 8. I2C SPECIFICATIONS PARAMETER Input Logic High, VIH Input Logic Low, VIL Input Logic Current, IIL SCL Clock Frequency NOTE: VDD = 5.0V/3.3V. SDA, SCL SDA, SCL SDA, SCL; 0.4V < Vin < 4.5V 0 100kHz TEST CONDITION MINIMUM TYPICAL 0.7 x VDD 0.3 x VDD 10A 400kHz MAXIMUM
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ISL6421A Typical Performance Curves
89 88 18.0V 87 EFFICIENCY (%) 86 85 84 83 82 81 50.0 150.0 250.0 350.0 IOUT (mA) 450.0 550.0 84 83 14.0V EFFICIENCY (%) 87 86 450mA 85 89 88 200mA
8.0
10.0
12.0 VIN (V)
14.0
FIGURE 4. EFFICIENCY vs LOAD CURRENT
FIGURE 5. EFFICIENCY vs VIN
TONE & VOUT (1V/DIV)
22kHz TONE (0.1V/DIV)
DSQIN (1V/DIV)
10s/DIV
0.2ms/DIV
FIGURE 6. 22kHz TONE
FIGURE 7. 22kHz TONE MODULATED BY DSQIN
VOUT (20mV/DIV)
VOUT (20mV/DIV)
VPWM (20mV/DIV)
VPWM (20mV/DIV)
2s/DIV
2s/DIV
FIGURE 8. RIPPLE VOUT = 14.0V
FIGURE 9. RIPPLE VOUT = 18.0V
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ISL6421A Typical Performance Curves
(Continued)
VOUT (1V/DIV) VPWM (1V/DIV)
VOUT (1V/DIV) VPWM (1V/DIV)
IOUT (0.2A/DIV)
IOUT (0.2A/DIV)
0.5ms/DIV
0.5ms/DIV
FIGURE 10. DYNAMIC RESPONSE VOUT = 19.0V
FIGURE 11. DYNAMIC RESPONSE VOUT = 14.0V
VGATE (2V/DIV)
VGATE (2V/DIV)
VDRAIN (10V/DIV)
VDRAIN (10V/DIV)
2s/DIV
2s/DIV
FIGURE 12. GATE AND DRAIN WAVEFORMS VOUT = 19.0V
FIGURE 13. GATE AND DRAIN WAVEFORMS VOUT = 14.0V
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FN9167.3 March 9, 2006
ISL6421A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 8 0.25 0.30 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.40 32 8 8 0.60 12 0.50 0.15 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN9167.3 March 9, 2006

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